1. Field
The present embodiments relate to electronic design automation (EDA). More specifically, the present embodiments relate to techniques for automatically snapshotting design states of EDA designs upon creating simulation results associated with the design states.
2. Related Art
Integrated circuit design often involves the use of schematics, which typically contain logical representations of components and wires in integrated circuits. EDA tools are typically used for creating schematics. For example, a schematic editor may allow a designer to create an electronic schematic of an integrated circuit. The electronic schematic may then be used by other EDA tools to simulate the operation of the integrated circuit, create a layout of the integrated circuit, and/or detect errors in the schematic.
In particular, EDA tools may verify the correct operation of the integrated circuit by providing simulators for the integrated circuit. For example, an EDA application may provide transistor-level simulation to verify the device-level accuracy of the schematic. The EDA application may also include a logic simulator that verifies the logic-level accuracy of the schematic. Finally, the EDA application may provide behavioral simulation of the schematic's architectural operation to verify the cycle-level and/or interface-level accuracy of the schematic.
Simulations may additionally facilitate the design of the integrated circuit by providing feedback regarding the integrated circuit's operation and/or performance. For example, a transistor-level simulation may be performed using the schematic and a set of design parameters and/or testbench parameters associated with the schematic. Results from the simulation may be used to update the schematic, the design parameters, and/or the testbench parameters, and a subsequent transistor-level simulation may be performed to determine the impact of the update on the integrated circuit's operation and/or performance. The alternating execution of simulations and updating of design parameters and/or testbench parameters may proceed until the desired simulation results are obtained.
Consequently, tighter integration of simulation and design environments within EDA tools may improve the ease and efficiency with which integrated circuits are designed.